1. Field of the Invention
The present invention relates to a semiconductor memory module device, and more particularly to a semiconductor memory module, wherein if a defective semiconductor device having at least one defect data line among a plurality of data lines is mounted to a module substrate, auxiliary pads are used to disconnect the defective data line and to maintain memory capacity and reduce manufacturing costs.
2. Description of the Prior Art
Due to the steady increase in memory capacity along with the current trend to incorporate microprocessor technology in electrical appliances, a plurality of semiconductor devices are mounted to a module substrate to form a semiconductor memory module for use in computers as a secondary memory device.
Memory modules using a conventional memory chip can be classified by memory capacity and the existence or the non-existence of error check and correction (hereinafter referred to as "ECC"). According to the existence or the non-existence of ECC, the memory module is classified as a binary 8 module (hereinafter referred to as "x8") provided with only an 8bit data transmission line, and a binary 9 module (hereinafter referred to as "x9") provided with an ECC memory and the 8bit data transmission line. According to memory capacity, the memory module is classified as 1Mbx8(9), 4Mbx8(9), 16Mbx8(9), etc.
Generally, the memory module formation method is widely used in semiconductor devices, and the 1Mx8(9) module having a simple structure will be taken as an example to assist the understanding of the memory module formation method.
The 1Mbx8 module loads eight semiconductor chips of 1 megabit(Mb) or two semiconductor chips of 4 megabit(Mb) on a single module substrate. The 1Mbx9 module loads nine semiconductor chips of 1Mb or two semiconductor chips of 4 megabit and one 1 megabit semiconductor chip on a single module substrate.
FIG. 1 is a block diagram showing one circuit arrangement of a 1Mbx9. As shown in FIG. 1, the semiconductor device comprises two 4Mb semiconductor chips 12 and one 1Mb semiconductor chip 14.
The 4Mb semiconductor chips 12 are connected to data lines D0-D7 at their output pins, and have input pins connected to a signal input line of a column address strobe (hereinafter designated as "/CAS") signal which becomes a refresh signal of a column address for operating the semiconductor chip and an input line of a row address strobe (hereinafter designated as "/RAS") signal which will be a row address refresh signal, respectively.
The 1Mb semiconductor chip 14 has an input pin connected to an input line of a CAS for parity (hereinafter designated as "/PCAS") signal for ECC. The 4Mb semiconductor chips 12 and 1Mb semiconductor chip 14 have input pins commonly connected to a write /W signal and to an address signal AB--AB.
Although a 1Mbx9 module using nine 1Mb semiconductor packages is not illustrated, that memory module is constructed similarly to that shown by the block diagram of FIG. 1. An example of such a memory module is disclosed in U.S. Pat. No. 4,727,513, wherein nine 1Mb semiconductor packages are mounted to one side of a module substrate. Insertion pins for connecting the module with an external circuit project from one side of the module substrate and the module includes decoupling capacitors for preventing electrical shock of the semiconductor packages.
Using this technique, electrical shock to the semiconductor packages can be prevented, but a defective semiconductor package having a defective data line cannot be used.
For example, in one package among the 4Mb packages each having four data lines if a failure occurs in any one data line, during the manufacturing process of the semiconductor package, the semiconductor chip or the package itself is defective and must be discarded thereby bringing about a significant loss to a manufacturer.
A defective semiconductor chip having a faulty data line, with the failure occurring during the manufacturing process of the semiconductor package, will now be described.
FIG. 2 is a plan view showing one example of semiconductor memory module device 20 for mounting the semiconductor device of FIG. 1. and FIG. 3 is a sectional view of the semiconductor device, taken along line III--III of FIG. 2.
Semiconductor memory module 20 represents one example of a 1Mbx9 module manufactured by Meyer Hoff Co. using a chip-on-board (COB) technique. As shown in FIG. 3, semiconductor memory module 20 has grooves 24, respectively spaced by a predetermined distance on module substrate 21 having wiring patterns (not shown) on both sides thereof, and pads 25, connected to the wiring patterns around grooves 24. Separate from pads 25, auxiliary pads 26 are connected in the same way as pads 25, and 4Mb semiconductor chips 22 are mounted inside of grooves 24 by means of the COB method.
The 4Mb semiconductor chip 22 is a center-pad chip in which a bonding pad is formed in the center portion of the semiconductor chip so as to be suitable for mounting by the COB method. Here, if any one data line among the four read/write data lines has a defect, semiconductor chip 22 becomes a defective semiconductor chip with a defect data line (hereinafter referred to as "DDL").
The bonding pads of semiconductor chips 22 and pads 25 formed on predetermined portions of module substrate 21 are connected by means of wires 28, and auxiliary pad 26 corresponding to the DDL is electrically connected to the bonding pads of the semiconductor chips.
That is, because semiconductor chips 22 are center-pad chips, auxiliary pad 26 nearest to the next data line of the DDL is connected by means of wire 28, so that the 1Mbx9 module is constructed by three 4Mb semiconductor chips.
Semiconductor chips 22 and wires 28 are shielded by package body 29 molded by an epoxy molding compound (hereinafter referred to as "EMC").
As shown in FIG. 2, pins 27 inserted into an external substrate are formed on one side of module substrate 21.
The manufacturing process of semiconductor memory module 20, constructed as above, will now be described in detail.
After semiconductor chips 22 are examined to check the DDL via an inspection process, the mounting areas of respective semiconductor chips 22 are determined, and then pads 25 and auxiliary pads 26 to be connected to the bonding pads of semiconductor chips 22 are determined, respectively. At this time, the bonding pads are connected to the nearest auxiliary pads 26.
Then, semiconductor chips 22 are inserted into grooves 24 in module substrate 21 so as to be mounted using an insulation adhesive and data with respect to the locations of pads 25 or auxiliary pads 26 connected to the bonding pads is programmed in a wire bonder.
After electrically connecting the bonding pads, pads 25 and auxiliary pads 26 by wires 28, module substrate 21 is mounted in a molding die to form the package body 29 for shielding semiconductor chips 22 and wires 28.
The conventional 1Mbx9 module of the Meyer Hoff Co. is formed by using three 4Mb semiconductor chips having one DDL, so that the module having 1Mb memory capacity performing the operation of the blocks described with reference to FIG. 1 is formed to reduce manufacturing cost, by using the defective chip rather than discarding it.
However, the above-stated method is disadvantageous in that the semiconductor chip is not manufactured as a center-pad chip, and a general semiconductor chip having its bonding pads on the periphery thereof cannot be utilized.
Moreover, the DDL must be checked before mounting the defective semiconductor chips, the auxiliary pads to be used must be determined, and then the data according to the bonding position of the wire bonder must be programmed one by one. Thus, the working efficiency is lowered and the yield is degraded.
Once the defect occurs, reworking is impossible which results in the whole module being defective, due to the reason that the semiconductor chip mounted via the COB method is molded by the EMC.
Furthermore, humid air from the external environment easily permeates into the interior of the package body, molded via the EMC, to cause failure such as disconnection of wires, thereby degrading reliability of the memory module.